The Challenges of Smart Innovation

Industrial technology is necessary to drive smart innovations that improve the interaction between humans and technology through smart, dynamic processing to static mediums

Unfortunately, these smart innovations come with a number of challenges that must be addressed before productizing the innovation.

One is the challenge of balancing maximum performance and power consumption. Industrial developers need devices that are capable of maximum performance at ultra-low power. Another is the challenge of achieving portability in a battery-powered system.

Similarly, commercial technology is revolutionizing portability through wearable devices that improve consumers’ interaction with the world around them. These devices tend to process, analyze and then summarize the data collected around the consumer. Just as with industrial technology, the common goal becomes extracting the most performance while using the least amount of power to enable battery operation.

While many processor architectures exist for developers to choose from, the choice is highly depended on the application. As the industrial and consumer technologies become smarter, they focus more and more on analytics to deliver results. Analytics tend to be highly parallel, mathematical calculations and data analysis that are best suited for DSP-based architecture. Due to the DSP architecture’s ability to focus on the parallelism of data manipulation and high-performance arithmetic processing units, it is the best approach to reduce active power consumption and improve battery life.

Inside DSP architecture

DSP architecture enables smart analysis of data that is fundamental to the industrial and wearable markets by enabling diverse algorithms with fast processing and predictable latency. These requirements are driven by the operator’s expectation to obtain useful information from the device in real time. To make it real time while conserving battery, the wearable architecture must accommodate low, predictable latency that will guarantee the timely delivery of the information.

DSP cores solve the latency requirement by utilizing predictable data paths and forgoing virtual memory managers that are commonly used in non-deterministic systems. The whole data path is designed to stream data with the lowest possible latency. By driving the latency down, the DSP can then spend less time actively managing data flow and thus reduce the power consumed from the battery. From the ground up, DSP cores have been developed and refined to support real-time processing without non-deterministic interruptions. Consumers expect the information to not only be real time, but also contain a useful summary of the data.

In addition to latency, another aspect of analytics is the actual analysis of the data. To reduce the power consumption, the device must be able to process the data quickly. Since processing the data usually involves mathematical computation, ideal architecture must be designed to enable quick parallel instructions with high computational efficiency.

DSP architecture accomplishes both through the use of single-instruction, multiple-data (SIMD) operations and high-efficiency multiply-accumulate operations. SIMD operations allow for high parallelism because they can apply the same algorithm to multiple data points at the same time and reduce the operating time of the algorithm. In turn, this will reduce the active power consumption and save battery life.

A lot of algorithms for analyzing real world data depend heavily on transforming the data through filters and transforms, such FIR, FFT and DCT. Filters and transforms boil down mathematically to summations of multiplications, which are greatly accelerated by multiply-accumulate operations. DSP cores are designed specifically for multiple-accumulates and provide the leading performance. Similar to SIMD, high-efficiency multiple-accumulate operations reduce the processing time and save active power consumption.

Outside DSP architecture

The DSP core does the heavy computational lifting, and it can be greatly enhanced through the SoC architecture around the core. Computational efficiency requires reliable connectivity into the device and fast data management inside the device. A well-designed DSP SoC can further improve the battery life by streamlining the connectivity and data flow.

Connectivity is extremely important to analytics in both industrial and consumer wearable applications as the algorithms depend on external data that must be piped into the device. The DSP SoC tends to include low-overhead and low-latency interfaces to get the data in quickly, such as SPI, I2C and SRIO. This enables fast transmission to improve battery life, while reducing pin count and size through the serial protocols.

Another way a DSP SoC can accelerate the performance and reduce battery power consumption is through the use of on-chip accelerators. The accelerators are optimized to perform a common task quickly while the DSP core idles or calculates in parallel. In a C5517 DSP from Texas Instruments, for example, Fast Fourier Transform (FFT) is a critical part of the algorithm used to extract useful information in applications like audio processing or voice recognition. In order to improve power consumption, the C5517 provides an on-chip FFT accelerator that can improve efficiency several times over other architectures such as Cortex-M4.

Conclusion

Among the available architectures, the DSP core and SoC provide the best balance between computational performance and power consumption. For industrial and consumer wearable applications that depend on battery life, DSPs allow for highly efficient processing to enable smart innovations. DSP devices can help developers create revolutionary technology by optimizing the processing capabilities and preserving battery life.

These optimizations are achieved through smart parallelism inside the computational engine, internal data flow architecture and external connectivity. When selecting a differentiating platform to develop smart battery powered applications, DSP is the right choice.